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INC7 Poster Abstracts


INC7 Posters - Europe

Advanced design framework for nanophotonic components

R. Baets; Ghent University, Department of Information Technology;
Sint‐Pietersnieuwstraat 4, 9000 Gent; Belgium

Design tools for nanophotonic integrated circuits do not yet show the maturity of standardized design frameworks that are adopted by the CMOS industry. The landscape is evolving quickly however. Photonic design tools are gaining functionality and are being integrated better. In designs where photonics and electronics are combined, the design tools also require interoperability with industrial software platforms like OpenAccess (used by Cadence, Synopsis and others).

At Ghent University/imec, we have developed the IPKISS software framework for efficient closed loop design of nanophotonic components.

All the steps in the design workflow are based on a single high‐level definition of the nanophotonic component in the form of a Python script.

The tools used in the design process are loosely coupled with the IPKISS core engine through a modular architecture. The IPKISS definition of a component is used to initialize and trigger the external tool, for example to interface a component's geometry with an electromagnetic simulator. This boosts efficiency and reduces manual errors. The open nature of the IPKISS framework allows a flexible integration of different tools and permits users to explore alternative approaches for a certain step in the design process. The design cycle steps are interlinked in a semi‐automated way, which allows to iterate efficiently over different parameter sets while reducing manual errors. IPKISS can export designs as GDSII files, but a layout interface with Cadence was also demonstrated as part of the European HELIOS project.

IPKISS allows to construct libraries of parametric photonic components for re‐use in later designs. The Python script contains an accurate, analytic description of the component, based on a set of parameters.

Such a description can be easily extended or modified, which allows to capitalize on earlier work, while remaining very flexible at the same time.


Moisture Barrier Properties of Micro- and Nano- Particle Filled Encapsulants

T. Braun, J. Bauer, K.-F. Becker, R. Aschenbrenner, K.-D. Lang

Fraunhofer Institute for Reliability and Microintegration
Gustav-Meyer-Allee 25, 13355 Berlin, Germany
phone: +49-30/464 03 244
fax.: +49-30/464 03 254

Polymer materials - mainly epoxy resins - are widely used in microelectronics packaging. They are estab-lished in printed circuit board manufacturing, for adhesives as die attach glues or for encapsulants as molding compounds, glob tops or underfill materials. Low cost and mass production capabilities are the main advantages of these materials. But like all polymers they cannot provide a hermetical sealing due to their permeability prop-erties. The susceptibility to water diffusion through the polymer and along the interfaces is a drawback for poly-mer materials in general, as water inside a microelectronic package might lead to softening of the material and to a decreasing adhesive strength and resulting delaminations close to solder bumps or wire bonds reducing pack-age reliability by decreasing the package structural integrity. During package reflow, the incorporated humidity might lead to popcorning, i.e. abrupt evaporation of humidity during reflow soldering. This effect is one major problem during plastic package assembly. The introduction of high temperature lead-free soldering processes has even increased this issue. Therefore, plastic packaging materi¬als with enhanced humidity resistance would in-crease package reliability during assembly and lifetime ideally without cost increase and with no changes in processing.

As filler particles have an important influence on the final material properties of microelectronic encapsul-ants, they are well suited for material modifications. Typically micro-sized silica particles are incorporated into the polymer matrix as the thermo-mechanical properties could be well adapted to reliable packaging demands. However, there are a lot of nano- and micro-sized filler particles with potential to enhance the humidity barrier properties of encapsulants. Working principles of these particles may range from large surface impact of nano-particles, barrier functionality due to stacked layer formation (nano-clays), highly hydrophobic particle surface and molecular water catcher function. Micro- and nano-sized SiO2, bentonite, zeolites, Al2O3, carbon black and carbon nano tubes have been selected for a systematic study. To evaluate the potential of such additives concern-ing moisture resistance particles are mixed with a microelectronic grade epoxy resin. Formulations are character-ized regarding their influence on humidity diffusion, absorption and desorption behavior. Different methods for characterization of the diffusion properties have been developed and applied for material analysis.

Plastic packaging materials for enhanced humidity barrier enhancement within microelectronic packages is gaining increased importance when considering the trend towards System in Package, where a multitude of com-ponents is encapsulated to form one miniaturized SiP that incorporates a large number of different material inter-faces and interconnects. These SiPs need to be protected from the environment by encapsulants layers with ever decreasing thickness and thus increased moisture barrier properties.


Dresden Fraunhofer Cluster Nanoanalysis

Dr. René Hübner 

Ten Fraunhofer Institutes and three faculties of the Technische Universität Dresden as well as Helmholtz-Zentrum Berlin cluster their competencies and cover the complete range of topics in the field of nanoanalysis. The institutes are flexibly linked and also cope with comprehensive project requirements.

Based on the vision to establish an internationally visible competence center for nanoanalysis as recognized partner for industry, the Dresden Fraunhofer Cluster Nanoanalysis is focused on ap-plied research and development in the field of nanoanalysis for discovering suitable technical and conceptual solutions, in particular:
  • Advancement of analysis methods,
  • Development of components and systems for new analysis techniques,
  • Development of application strategies for advanced analysis methods and systems,
  • Consultation and accomplishment of services in the field of analysis for high-tech com-panies.
The Dresden Fraunhofer Cluster Nanoanalysis covers the following application areas:
  • Micro-, nano-, and optoelectronics,
  • Renewable energy sources,
  • Lightweight construction and functional materials.
For further information, please visit the web site at


Nanotechnologies at Fraunhofer ENAS

The Fraunhofer Institute for Electronic Nano Systems ENAS focuses on research and development in the field of smart systems integration by using micro and nano technologies. Special attention is paid to ultrathin functional films as well as application of nano materials.

The joint micro and nano electronics group of Fraunhofer Institute for Electronic Nano Systems ENAS and the Center for Microtechnologies at Chemnitz University of Technology delivers solutions for materials and processes, as well as integration and simulation:
  • Metallization for micro and nano electronics
  • Low-k and ultra low-k dielectrics
  • Air gaps for low parasitic capacitances in nano interconnect systems
  • Process and equipment simulation
  • Interconnect system modelling
  • Process development, e.g.:
    • Chemical mechanical polishing (CMP)
    • Chemical vapour deposition (CVD)
    • Atomic layer deposition (ALD)
    • Dry and wet etching / cleaning

In order to make use of nano effects in MEMS packaging, the department System Packaging of Fraunhofer ENAS investigates and applies nano scaled intermediate layers and layer systems. The aim of this work is to achieve permanent and hermetically sealed joints between two wafers, using the lowest temperature impact on the system.


Prof. Dr. Stefan E. Schulz
Fraunhofer ENAS
Technologie-Campus 3,
09126 Chemnitz


3D Wafer Level System Integration

M. Juergen Wolf

Fraunhofer Institute for Reliability and Microintegration IZM-ASSID | Ringstrasse 12, 01468 Moritzburg, Germany

* E-mail of corresponding author:

According to the technical requirements of future microelectronic products 3D system integration becomes one of the main drivers whereas 3D wafer level technologies are among the most promising technologies for heterogeneous system integration.

The center “All Silicon System Integration Dresden” (ASSID) with a 300 mm wafer process line has been established as part of Fraunhofer IZM to meet these specific challenges in performance, functionality and scaling requirements. Our new center has a state-of-the-art cleanroom facility and is equipped with a complete 300 mm process line for TSV formation, TSV post-processing on wafer front- and backside, 3D device stacking assembly, as well as testing and failure analysis. ASSID activities are embedded into the overall Fraunhofer IZM’s 3D system integration strategy. The facility, infrastructure and know-how are especially tailored to partners in industry for research and development projects, as well as prototype realization.

Fraunhofer IZM is a partner in different national, European and worldwide industrial and scientific networks for 3D System Integration, e.g. EMC 3D, HTA, Silicon Saxony, Euripides.



INC7 Posters - Japan

Tsukuba Innovation Arena for Nanotechnology (TIA-nano) Update

M.Watanabe1,2, N.Sano1,3, K.Nakamura1,4, K.Abe1,3, K.Ono1,3, K.Miura1,3, T.Kadohira1,4, N.Arai1,4, A.Watanabe1,4, E.Watanabe1,4, K.Sakamoto*1,2, Y.Seki1,2, K.Nakayama1,2, F.Takano1,2, A.Ogasawara1,2, M.Morimoto1,2, N.Yamamoto1,2, T.Yoshimura1,5 and R.Aibe1,5

1 Secretariat of Tsukuba Inovation Arena for Nanotechnology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
2 National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
3 University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8577, Japan
4 National Institute for Materials Science (NIMS), 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047, Japan

5 Nippon Keidanren, 1-3-2, Otemachi, Chiyoda-ku, Tokyo 100-8188, Japan

* E-mail of corresponding author:

The Tsukuba Innovation Arena for Nanotechnology (TIA-nano) is aimed at creating a global research and education complex for nanotechnology in Tsukuba, where the world’s most advanced nanotechnology research facilities and personnel are gathered. This will be done with the support of the government and under the leadership of AIST, NIMS and University of Tsukuba, and with the participation of leading companies in the nanotechnology industry. TIA-nano has drafted a medium-term plan from fiscal 2010 to fiscal 2014. It shows specific visions to be achieved by TIA-nano over the next five years as a global industry-academia-government collaboration complex founded on a platform formed by public research and education organizations, along with action plans to achieve these visions. Based on this medium-term plan, TIA-nano will promote initiatives with the goal of promoting the prosperity of Japan as an advanced manufacturing nation and solving global problems. The great east Japan earthquake hit the TIA-nano’s core infrastructures. Present reconstruction status will also be reported.


Development of Core Technologies for Green Nanoelectronics

Naoki Yokoyama1, Toshihiko Kanayama2, Tsutomu Tezuka1, Hiroyuki Ohta1, Kenji Hata3, Shintaro Sato1, Mizuhisa Nihei1, Toshimichi Shintani1, and Junji Tominaga4

1Green Nanoelectronics Center, National Institute of Advanced Industrial Science and Technology, West 7A 16-1 Onokawa, Tsukuba, Ibaraki 305-8568, Japan
2 National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
3Nanotube Research Center, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
4Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba Central 4, 1-1-1 Higashi, Tsukuba, Ibaraki 305-8568, Japan

* E-mail of corresponding author:

It is a critical requirement to decrease the power consumption of the IT devices on a different scale to put the prosperity of the global community on a low-carbon path and maintain continuous development of the information society. In the Collaborative Research Team Green Nanoelectronics Center, about 60 excellent researchers get together to develop the core technologies for decreasing the power consumption of semiconductor LSI which makes up the IT devices, to one tenth at least, eventually down to one hundreds.

Three main research assignments are: (1) development of low voltage operation CMOS technologies, (2) development and application of nanocarbon materials, and, (3) the material R&D of the phase-change memory devices. Fortunately, our study proposal was chosen as one of the Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program), and became eligible to accomplish the research as one of the projects of the Nanoelectronics base of "Tsukuba Innovation Arena - TIAnano". Our project aims to expansive target by linking with other Nanoelectronics projects, so that we can bring up leaders of the next generation. This paper describes current status of our research activities.


Low-power Electronics Association & Project (LEAP) and its role in the development of low-power devices

Naotaka Sumihiro, Toshihiro Sugii, Takashi Takenaga, Norikatsu Takaura, Hiromitsu Hada, Tadashi Sakai, Nobuyuki Sugii, Shin’ichiro Kimura

Low-Power Electronics Association & Project,
West 7A, 16-1 Onogawa, Tsukuba, Ibaraki 305-8669, Japan
* E-mail of corresponding author:

Reduction of power dissipation of IT and electronics equipment is the key issue to achieve low-carbon society. For this purpose, Low-power Electronics Association & Project (LEAP), inaugurated on May 21, 2010, by 9 member companies started “Ultra low voltage device project for low-carbon society” on Aug. 6, 2010, under contract with Ministry of Economy, Trade and Industry. As of May 2011, the number of members is 10.

This is a 5-year project that aims to develop new non-volatile backend memories and switching devices having new functions, interfaces and flexibility for IT equipment, taking advantage of 300-mm Si facilities in Tukuba. In addition, it aims to develop new basic technologies such as SOI transistors characterized by small variability and carbon interconnects with low resistivity. The backend memories and switching devices utilize the change of resistance of materials as a basic operation mechanism and they are buried during backend steps. Since the resistance change is used, the devices have, in principle, potential ability to enable low voltage operation.

The project is one of the nano-electronics R&D projects in Tsukuba Innovation Arena (TIA). TIA consists of networked projects on 6 topical areas conducted by national institutes, universities, research consortiums, and industries. The project is now funded by NEDO (New Energy and Industrial Technology Development Organization.)


Research and Development of Ultra-low Power Spintronics-based VLSIs

Tetsuo Endoh
Deputy Director, Professor (Research-promotion leader)
Center for Spintronics Integrated Systems
Tohoku University

Logic integrated circuit, where intelligent systems are integrated on a single chip die, is the key technology in modern society, determining the quality of various systems as well as the social infrastructure. Ground-breaking innovation that forces paradigm shift now rarely occurs in the designing and manufacturing technologies of VLSI which have already seen tremendous growth. However, based on the achievements of past projects, it has become evident that the fusion of nonvolatile spintronic devices which retain memory without energy usage with the semiconductor integrated circuits will bring about a revolutionary change.
Under the project "Research and Development of Ultra-low Power Spintronics-based VLSIs" (PI: Hideo Ohno), which started in March 2010 and is supported by JSPS's "Funding Program for World-Leading Innovative R&D on Science and Technology" (FIRST), this program aims to contribute to the realization of a low-carbon and energy-saving society and to the strengthening of international competitiveness in the field of next generation VLSIs, through the development of innovative energy-saving logic VLSIs that fuse spintronics devices and logic-integrated circuits under the collaboration among industries, universities and government focusing on these technologies. In this poster, the research activity of our program will be presented.


Towards fully integrated laser-induced fluorescence (LIF) detection devices for point-of-care microfluidic biochemical analysis

Toshihiro Kamei1*, Takeshi Kobayashi1, Hideki Takagi1, Ryutaro Maeda1

1 Ubiquitous MEMS and Micro Engineering Research Center, National Institute of Advanced Industrial Science and Technology, 1-2-1 Namiki, Tsukuba, Ibaraki 305-8564, Japan
* E-mail of corresponding author:

Miniaturization and integration of laser-induced fluorescence detection system is prerequisite to exploit potential point-of-care benefits of microfluidics. Most of integrated fluorescence detectors, however, suffer from high limit of detection (LOD) compared to conventional optical system that consists of discrete optical components, which is mainly due to higher laser light scattering of integrated optics rather than detector sensitivity. We have reduced background (BG) photocurrent of an integrated hydrogenated amorphous Si (a-Si:H) fluorescence detector due to laser light scattering, significantly improving a LOD and demonstrating capability of detecting single molecular DNA when combined with polymerase chain reaction (PCR). Now we are working towards integration of blue-green InGaN laser diode (LD)/LED and micro-optical system to construct fully integrated LIF devices. Although advantages using a-Si:H include monolithic integration on heterogeneous materials, we are pursuing for alternative approach such as surface activated wafer to wafer (chip) bonding. The integrated a-Si:H-InGaN based detection-excitation device will be capable of high sensitivity detection of visible fluorescence emitted from practical labeling dye, making it ideal for application to point-of-care microfluidic biochemical analysis.


Developing strategy for assessing and managing risk of industrial nanomaterials

Atsuo Kishimoto1,2,*, Hisashi Hashimoto1, Katsuhide Fujita1,2, Isamu Ogura1,2

1 Technology Research Association for Single Wall Carbon Nanotubes, 16-1 Onogawa Tsukuba, Ibaraki 305-8569, Japan
2 Research Institute of Science for Safety and Sustainability, National Institute of Advanced Industrial Science and Technology, 16-1 Onogawa Tsukuba, Ibaraki 305-8569, Japan
* E-mail of corresponding author:

Industrial nanomaterials should be proved that it is regarded as safe, when they are introduced into the commercial market. But, the introduction of laws and regulations which concern emerging technologies often lag behind the development of the technologies. Therefore, business enterprises in the nanotechnology industry are facing the need to carry out risk assessment by themselves. “NanoSafety” of the Tsukuba Innovation Arena (TIA) was created in order to develop a strategy to assist responsible development of nanotechnology. It presents a framework for risk assessment and management of manufactured nanomaterials, exemplifying the ways of addressing safety issues in the phase of R&D. “NanoSafety” places its focus on carbon nanotubes (CNTs) in particular, and develops techniques for ensuring their life-cycle safety. For exposure assessment, “NanoSafety” develops a framework combining an on-site measurement method and a prediction method. For toxicity assessment, it develops a method taking full advantage of in-vitro testing. These methods are simple, rapid and cost-effective. Public acceptance, in addition to assessing and managing risks, is indispensable for bridging CNTs to society. It is important to establish a way of communicating the result of assessment to various stakeholders.


Open Innovation Tactics Specialized for Green Functional Oxide Nanotechnology

Hisashi SHIMA and Hiro AKINAGA

Innovation Center for Advanced Nanodevices (ICAN),
National Institute of Advanced Industrial Science and Technology (AIST),
1-1-1 Umazono, Tsukuba, Ibaraki 305-8568, Japan
* E-mail of corresponding author:

Green functional oxide nanotechnology is becoming imperative because advanced electronic devises based on functional oxide materials are expected to promote the deep slashes of the information-technology (IT)-related energy consumption. Therefore, the framework arranged to accelerate the research and development activities concerned with such advanced devices are essential for the sustainable development of this IT society.

In 2010, we have launched the platform for green functional-oxide nanotechnology (GreFON). Non-volatile random access memory, transistor, and solar cell devices built with transition metal oxides are intensively developed as promising main targets of GreFON. In addition to this first mission of GreFON, this platform is required to be an open innovation hub organized especially for oxide electronics. For this critical second mission, GreFON participates in the nation-wide low-carbon research network (LCnet) program whose architecture is to provide researchers and engineers in the academic and industrial arena with the opportunities to utilize the most advanced equipments and facilities inside the network.

In this presentation, our concepts and management strategies of GreFON as well as development examples of functional oxide based devices and their operating performances will be introduced.


Highly Efficient Dye-Sensitized Solar Cells

Liyuan Han*, Ashraful Islam, Masatoshi Yanagida

Advanced Photovoltaics Center, National Institute for Materials Science
1-2-1 Sengen Tsukuba, Ibaraki, 305-0047, Japan
* E-mail of corresponding author:

Dye-sensitized solar cells (DSCs) have been widely investigated as a next-generation solar cell because of low manufacturing cost. In this presentation, strategy for improving efficiency of DSCs was reported. The method for improvement of shirt circuit density (Jsc), open circuit voltage (Voc) and fill factor (FF) were investigated based on the equivalent cirsuit. It is found that the series-internal resistance decreases with increase of the roughness factor of the counter electrodes, the decrease of the thickness of the electrolyte layer and the sheet resistance of the transparent conducting oxide. For the purpose of improving Jsc, dependence of incident photon to current conversion efficiency (IPCE) spectra on haze of TiO2 film was investigated. IPCE is widely increased with increase of the haze of TiO2 film, especially in infrared region. An overall conversion efficiency of 11.2% was achieved which is the highest confirmed efficiency.


The activities of Nanotechnology Network Program in Japan

K. Furuya, K.Hirahara and T. Noda
Center for Nanotechnology Network, National Institute for Materials Science
1-2-1 Sengen, Tsukuba, Ibaraki 305-0047, Japan

The “Nanotechnology Network Program” was started in 2007 following the “Nanotechnology supporting program (2002 – 2006)” by the Minister of Education, Culture, Sport, Science and Technology, Japan (MEXT). The program’s main mission is by providing nanotechnology research personnel from the industrial, academic and public sectors with opportunities using cutting-edge facilities and advanced equipments to accelerate interdisciplinary researches leading to innovation.

Twenty six institutes and universities were selected and grouped into 13 centers across the country. Individual centers have their own strengths and unique programs, and offer services in at least one of four areas: “Nano- characterization and Analysis”, “Nanofabrication”, “Molecular Synthesis and Analysis”, and “Extreme Conditions”.

The average number of approved projects are about 1,400/year for joint researches and share-use of equipments. The typical titles of the projects in 2009 are as follows: -- *host institutes

1) Study of fabrication of three dimension optical polymer by dynamic maskless lithography technique (Optmate Co. Ltd., Research Institute for Electronic Science and Hokkaido University*)

2) Nanostructural analysis of multi-ferroics materials (JST-ERATO Tokura Multi-ferroics Project and National Institute for Materials Science*)

3) Instant implementation of carbon nanotube field emitters (The University of Tokyo* and DAINIPPON SCREEN MFG. Co., Ltd.)

4) Microdevice-based fabrication of gene delivery nanosystem (Kyoto Pharmaceutical University, Hokkaido University and Nagoya University*)

5) Microfluidic chip for Single molecular detection (Toyota Technological Institute* and ESPINEX, Inc.)

In the users, about 15 % comes from industries, 20 % from national institutes and 65 % from universities. All of the results obtained with this program have to be published as open literatures and press to promote common understanding of nanotechnology.


Characterization of High-k Gate Stacks by EBIC Technique

Jun Chen1, Takashi Sekiguchi1, *, Naoki Fukata1, Motoyuki Sato1, Masami Takase1, Ryu Hasunuma2, Kikuo Yamabe2, Keisaku Yamada2, Toyohiro Chikyo1

1 National Institute of Materials Science, 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan
2 Tsukuba University, 1-1-1 Tennoudai, Tsukuba, Ibaraki 305-8573, Japan
* E-mail of corresponding author:

When integrating CMOS with high-k gate dielectrics, a key issue is to find compatible gate electrode material from the viewpoints of both work function and reliability issue. The interaction between gate electrode materials and high-k dielectrics may cause performance degradation and serious reliability issue. We have recently applied electron-beam-induced current (EBIC) technique for the visualization of leakage sites in high-k gate stacks with hafnium silicate gate dielectrics. The occurrence of initial leakage sites was affected by the Si-well type and gate electrode material. Stress-induced leakage sites were also detected under combinational time-dependent dielectric breakdown (TDDB) and EBIC measurements. It is revealed that progressive breakdown is not related to the enlargement of defect size, but due to the increase of defect number. The breakdown behavior of high-k dielectric strongly depends on bias polarity and gate electrode material. Progressive breakdown occurs under positive bias stress and abrupt breakdown under negative bias stress. The former is frequently observed in silicon-based gates but not in metal gates.


New materials research for future nano electronics in NIMS

Toyohiro Chikyow, Toshihide Nabatame,Takahiro Nagata, and Michiko Yoshitake
Advanced Electric Materials Center, National Institute for Materials Science
1-1 Namiki Tsukuba Ibaraki 305-0044, Japan

NIMS has been focusing on "Nanotechnology-Driven Advanced Materials Research" with the aim of achieving world-level pioneering technical innovation NIMS is engaged in fundamental research and development of materials utilizing nanotechnology. Practically NIMS has been promoting materials research for future gate stack materials, such as high-k dielectric, metal gate materials and their interface controlling.

To accelerate new materials discovery, we have been developing the “high throughput materials synthesis and characterization with combinatorial methodology” for the new materials discovery. In this process, at first calculation plays critical role in materials design. Then the practical synthesis and characterization are demonstrated. With this materials exploration concept, recently we found a new gate oxide which had a direct contact to Si and metal gate materials which was an amorphous alloy with the work function tuning. By combinatorial screening, we found that CeAlSiOx could have a direct contact to Si and the dielectric constant was 28. Also in changing the metal gate to control the work function , the flat band shift corresponded to the work function change, meaning that there was not “Fermi level pinning “ at metal/CeAlSiOx interface. metal alloys of TaC-Y were synthesized on HfO2 with different composition by sputtering to control amorphous structure and work function at the same time. In this experiment, we demonstrated to work function tuning in 0.8 eV, keeping amorphous structure.

As another example, we demonstrated a Cu atomic switching device using HfO2 as the host oxide.
As the combinatorial synthesis provides a systematic character change according to the composition, unexpected results sometimes come along with the aimed results. This process is called as “new materials discovery loop” which gives us serendipity in the materials screening.

In this presentation, NIMS activities in nano materials research with several examples are shown.


Our Research Activity on Nano-Scaled Electronic Devices Based at Tsukuba-Site ~ Property Fluctuation of MOSFETs ~

Kenji Ohmori1,2*, Toyohiro Chikyow3, Kenji Shiraishi1,2, Keisaku Yamada1,2

1 Graduate School of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8573, Japan

2 Core Research of Evolutional Science & Technology, Japan Science and Technology Agency (JST-CREST)

3 Advanced Electric Materials Center, National Institute for Materials Science, 1-1 Namiki, Tsukuba, Ibaraki 305-0044, JAPAN

* E-mail of corresponding author:

The fluctuation of metal-oxide-semiconductor field-effect-transistor (MOSFET) characteristics is one of the most formidable issues as the size of devices scales down. The static fluctuation refers the variability of threshold voltage and drain current, while the dynamic fluctuation includes random telegraph signal (RTS) and 1/f flicker noise.

We have revealed that for reducing static variability in metal/high-k gate stack structures, controlling the crystal structure in the metal gates are essential. We proposed a carbon incorporation technique for reducing the crystal grain size and thus, demonstrated the improvement of variability (K. Ohmori et al., IEDM 2007, IEDM 2008). We are currently focusing dynamic properties, i.e., noise in MOSFETs. We present that the static variability derived from a number of transistors is closely related to the dynamic fluctuation, which can be obtained from a single transistor.

In order to investigate those fluctuations, obtaining state-of-the-art MOSFETs with leading edge technology is significantly important. For this purpose, we have been collaborating with the organizations, which, for example, possess 12-inch Si wafer process facilities. In addition to the results from scientific research on fluctuation study, the synergistic effects through the research projects (High-k Net, JST-CREST) and collaboration among universities, national laboratories, and companies will be presented.


Our Research Activity on Nano-Scaled Electronic Devices Based at Tsukuba-Site ~ Property Fluctuation of MOSFETs ~

Kenji Ohmori1,2*, Toyohiro Chikyow3, Kenji Shiraishi1,2, Keisaku Yamada1,2

1 Graduate School of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8573, Japan
2 Core Research of Evolutional Science & Technology, Japan Science and Technology Agency (JST-CREST)
3 Advanced Electric Materials Center, National Institute for Materials Science, 1-1 Namiki, Tsukuba, Ibaraki 305-0044, JAPAN
* E-mail of corresponding author:

The fluctuation of metal-oxide-semiconductor field-effect-transistor (MOSFET) characteristics is one of the most formidable issues as the size of devices scales down. The static fluctuation refers the variability of threshold voltage and drain current, while the dynamic fluctuation includes random telegraph signal (RTS) and 1/f flicker noise.

We have revealed that for reducing static variability in metal/high-k gate stack structures, controlling the crystal structure in the metal gates are essential. We proposed a carbon incorporation technique for reducing the crystal grain size and thus, demonstrated the improvement of variability (K. Ohmori et al., IEDM 2007, IEDM 2008). We are currently focusing dynamic properties, i.e., noise in MOSFETs. We present that the static variability derived from a number of transistors is closely related to the dynamic fluctuation, which can be obtained from a single transistor.

In order to investigate those fluctuations, obtaining state-of-the-art MOSFETs with leading edge technology is significantly important. For this purpose, we have been collaborating with the organizations, which, for example, possess 12-inch Si wafer process facilities. In addition to the results from scientific research on fluctuation study, the synergistic effects through the research projects (High-k Net, JST-CREST) and collaboration among universities, national laboratories, and companies will be presented.


Enhanced Mobility over Universal Mobility in Silicon Nanowire Transistors in Less Than 10nm Scale

Toshiro Hiramoto, Jiezhi Chen, and Takuya Saraya
Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
Tel/Fax: +81-3-5452-6263, Email:

A silicon nanowire MOSFET is a promising structure for future VLSIs because of its high short channel effect immunity. When the width of nanowire is scaled down to the nanometer regime, transport properties are strongly affected by the quantum confinement effects. In this study, systematic measurements on electron and hole mobility in silicon nanowire transistors on (100) SOI substrate have been performed. Gate-all-around (GAA) silicon nanowire transistors with the [110] direction were fabricated by electron beam lithography and dry etching. The nanowire height is 4 - 10nm and the minimum nanowire width is shrunk to 5nm. In order to evaluate nanowire mobility accurately, multiple parallel nanowires were fabricated and mobility was characterized by advanced split CV method.

Measurement results are summarized below. In nanowire NFETs, mobility is kept almost constant as the nanowire width is narrowed but the mobility degradation is found when the width is 5nm. In nanowire pFET, on the other hand, higher mobility than (100) universal mobility is clearly observed in nanowires with width of less than 15nm and even in 5nm-wide nanowire. The maximum mobility is observed 9nm-wide nanowire, which is 2.3 times higher than the universal curve. The origins of the mobility enhancement are side-surface effect and subband modulation.

Acknowledgement: This work was supported by the Nanoelectronics Project by NEDO.


Observation of Pauli-Spin Blockade and Single-Electron Regime in Silicon Coupled Quantum Dots

Tetsuo Kodera1,2,3*, Kousuke Horibe1, Tomohiro Kambara1, Gento Yamahata1, Ken Uchida4, Yasuhiko Arakawa2,5, Shunri Oda1

1 Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1-S9-11, Ookayama, Meguro-ku, Tokyo, 152-8552, Japan.
2 Institute for Nano Quantum Information Electronics, the University of Tokyo, 4-6-1, Komaba Meguro-ku, Tokyo, 153-8505, Japan.
3 PRESTO, Japan Science and Technology Agency (JST), Kawaguchi, Saitama, Japan.
4 Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1-S9, Ookayama, Meguro-ku, Tokyo, 152-8552, Japan.
5 Institute of Industrial Science, the University of Tokyo, 4-6-1, Komaba, Meguro-ku, Tokyo, 153-8505, Japan
* E-mail of corresponding author:

Control of electron spin states in quantum dots (QDs) has recently attracted much interest toward quantum information devices. Especially in silicon, electron spins have been predicted to have long coherence time due to small hyperfine coupling between electron spins and nuclear spins.

For coherent control of electron spins, it is essential to confine a single electron in a QD and to detect changes of the electron occupation via a charge sensor near the QD. However, achieving single-electron occupation in silicon QDs is challenging because of relatively large electron effective mass and small tunneling rates.

In this work, we propose a novel device structure and its fabrication techniques for lithographically-defined silicon QDs. We fabricated coupled QDs utilizing electron beam lithography, reactive ion etching, and oxidation, in a metal-oxide-semiconductor structure on a non-doped silicon-on-insulator (SOI) substrate. One of the advantages of our device is that well-defined confinement potential and small QDs can be obtained. The other advantage is that the lateral confinement is expected to work efficiently for the formation of QDs since the in-plane effective mass of (100) silicon confined normal to the surface is light. We then succeeded in observing a single-electron regime in the QD and spin-related tunneling phenomena.


Experimental Study on Subband Structures and Hole Transport in (110) Si pMOSFETs under High Magnetic Field

Tsunaki Takahashi1*, Tetsuo Kodera2, Shunri Oda2, and Ken Uchida1,3

1 Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1-S9-12, Ookayama, Meguro-ku, Tokyo 152-8552, Japan
2 Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1, Ookayama, Meguro-ku, Tokyo 152-8552, Japan
3 PRESTO, Japan Science and Technology Agency (JST), 4-1-8 Honcho Kawaguchi, Saitama 332-0012, Japan
* E-mail of corresponding author:

The band structures and carrier transport in (110) Si pMOSFETs are thoroughly studied over a wide temperature range under high magnetic fields. In (110) pMOSFETs, the degenerate hole bands in bulk Si are separated into the higher energy band (H band) and the lower energy band (L band). The energy difference between these bands, ΔE, is experimentally evaluated. The effective masses of each band are directly obtained from the Shubnikov-de Haas (SdH) oscillation analysis. It is demonstrated that mobility in the higher energy band is worse than that in the lower energy band, resulting in sharp mobility drop at higher surface hole density and a clear hump in Id-Vg characteristics at low temperatures of less than 20 K. The higher mobility in the L band and the large L-band occupancy due to the large ΔE contribute to the excellent performance of (110) pMOSFETs. However, because finite holes still populate in the H band, it is important to minimize the H-band contribution for the improvement of the performance of (110) pMOSFETs.


Evaluation of Electrical and Optical Property and High-Density Assembly of Nano-Crystalline Silicon Dot Array for Device Application

Yoshifumi Nakamine*, Ken Someno, Hiroki Nikaido, Masahiro Kouge,
Tetsuo Kodera, Ken Uchida, Mutsuko Hatano, and Shunri Oda

Quantum Nanoelectronics Research Center and Department of Physical Electronics,
Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8852, Japan
* E-mail of corresponding author:

Nano-crystalline Silicon (Nc-Si) is a promising material for applications of high electron mobility thin-film transistors and high-efficiency solar cells. We have successfully prepared nc-Si dots with very uniform size distribution by a very high frequency (VHF) plasma process. In addition, we have obtained phosphorus doped nc-Si dots. Nc-Si ink of nc-Si is easily fabricated by our nc-Si fabricating system. Therefore, the solution process could be adopted for some electrical and optical device applications. Solution process is promising since fabrication costs of devices are less expensive using printing processes. However, technologies for more precise control of size of nc-Si dots and high density assembly are required for some device applications. In this poster, evaluation of electrical and optical properties and high-density assembly of nc-Si dots array are reported. The thin-film transistor structures are fabricated for measuring some electrical properties of nc-Si dot arrays. In addition, it is observed that the band gap is increased due to quantum size effect by decreasing the size of nc-Si dots through photoluminescence measurements. Finally, dip-coating and langmuir-brodgett method which are promising for high density assembly of nc-Si dots array are reported.


Synthesis of small-diameter Ge NW at low temperature for electron device application

Marolop Simanullang1*, Koichi Usami1, Tetsuo Kodera1, Ken Uchida2, Shunri Oda1

1 Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8552, Japan
2 Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8552, Japan
* E-mail of corresponding author:

Nanowire is one-dimensional structure that usually has less than 40 nm in diameter. Nanowire has attracted attention for the last decade due to their great potential for nanoscale electronic, photonic, and sensing devices. Ge has higher electron mobility than Si and among the well known semiconductors such as Si, GaAs, InAs, and InSb, Ge has the highest mobility of hole, making Ge promising for faster switching devices. Ge also has relatively large excitonic Bohr radius (24.3 nm), allowing quantum size effects to be observed in relatively large structure and at high temperature.

We have grown Ge NWs from GeH4 with single step-temperature technique via VLS mechanism in CVD reactor by varying temperature (300oC, 280oC, and 260oC) and equivalent thickness of Au nanoparticles (0.1 nm, 0.3 nm, 1 nm, and 3 nm). Ge NWs grown at 300oC tend to be tapered, but Ge NWs grown at 280oC and 260oC tend to be straight. Ge NW with diameter as small as ~3 nm has been grown at 260oC from 0.1-nm-thick Au nanoparticles, offering opportunity to fabricate high-performance p-type ballistic Ge NW transistor and to observe quantum confinement effect.


Green and Medical Nanotechnologies at Nara Institute of Science and Technology (NAIST)

Yoshihiro Todokoro
Center for Industry-Government-Academia Collaboration
Nara Institute of Science and Technology
8916-5, Takayama, Ikoma, Nara 630-0101 Japan
Phone: +81-743-72-5191 Fax: +81-743-72-5194

As a Japanese national university consisting solely of graduate schools that specialize in teaching and research in information, biological, and materials sciences, we have been tackling cutting-edge problems at the frontiers of science in an environment of interdisciplinary and international cooperation, and have achieved impressive results. Our tradition of working with industry and Government, and our strength in intellectual property management has enhanced our position in research and education. NAIST has been ranked first evaluated by MEXT in terms of research, education, and management among Japanese national universities during six fiscal years (2004-2009). Intellectual property management and technology transfer are effectively coordinated through an Industry-Government-Academia Collaboration group.

This presentation overviews some innovative research activities of Green and Medical Nanotechnologies combined with information technology, material technology and biological sciences. Fields of study in Green Nanotechnologies include photovoltaics including OPV, photonics research (photon-mode molecular memory, all optical buffer memory, and display device), and green and dependable device and LSI design (SiC device, low power MPU and design for test). Fields of study in Medical Nanotechnologies include medical imaging (surgery simulation, MRI medical imaging), medical devices (artificial retina, ultrasonic angioscope, and cataract inspection), and medical materials (bio-compatible materials, PDT materials, and regenerative tissues).


High-Q Micromechanical Resonators using Thin Film Encapsulation

Yasuyuki Naito1, Philippe Helin2, Kunihiko Nakamura1, Jeroen De Coster2,

Luc Haspeslagh2, Keiji Onishi1, Harrie A. C. Tilmans2

1 Advanced Devices Development Center, Panasonic Corporation, 1006 Kadoma, Kadoma
City, Osaka 571-8501, Japan

2 Imec, Kapeldreef 75, B-3001 Leuven, Belgium

* E-mail of corresponding author:

Silicon-resonator based oscillators provide an attractive alternative to replace conventional frequency control devices and timing devices that are based on high quality factor (Q) resonators such as quartz crystal, piezoelectric ceramic and SAW. Quartz crystal resonators display high frequency stability but are difficult to be miniaturized and cannot offer an integrated solution. Silicon MEMS resonators on the other hand offer enhanced miniaturization, low susceptibility to shock and vibration, and, higher integration over conventionally used quartz crystal resonators. High-Q MEMS resonators with low motional resistance and low DC bias are advantageous to attain high frequency accuracy (and stability) of a reference oscillator with low power consumption (by the sustaining amplifier and the charge pump). This paper reports on an SOI-based 20MHz MEMS torsional resonator, wafer-level packaged using SiGe thin film and hermetically sealed using Al sputtering at 1Pa. The packaged resonators display a high Q-factor (220,000) and a low motional resistance for low DC bias. Successful operation of a CMOS-based oscillator using the MEMS torsional resonator as the frequency determining element was demonstrated.


Pico Liter Dispenser with Needle and Tube for Repair Systems

Yoshiyuki Kato1*, Sadayuki Takahashi1, Yuuka Irie1, Hisayuki Aoyama2,

1 Applied Micro Systems Inc. , SVBL302, University of Electro-Communications,
1-5-1 Chofugaoka, Chofu, Tokyo 182-8585, Japan
2The University of Electro-Communications, 1-5-1 Chofugaoka, Chofu, Tokyo 182-8585, Japan
* E-mail of corresponding author:

There are two kinds of method for dispensers which spread a drop of liquid. One is an inkjet method and the other is a pneumatic method dispenser. The former can spread a very small amount of liquid drop such as 1 pl(pico liter), but can spread only a low viscosity liquid drop of 1 to 15 mPa.s(cP) . The latter, on the other hand, can spread a high viscosity liquid drop, but an amount of liquid drop is more than 1,000 pl.

In our group, the new style dispenser with the performance of an ultra small dispensing amount such as several pico liters with high viscocity has been developed with the help of advanced micro mechatronics technologies. The new method dispenser transcribes an ultra small liquid drop which is attached to the thin needle tip to the substrate. This dispenser can allow to dispense a liquid drop with viscosity liquid of 1 to 350,000 mPa.s(cP).

This newly developed dispensers based on the new principle will be expected to apply to FPD (Flat Panel Displays) repair instruments for the defects of color filter and circuit wiring pattern in the liquid crystal displays, very little adhesive agent dispensers and so on.



INC7 Posters - USA

Charge transport and absorption study of metal nanoparticle plasmonics for organic photovoltaics*

Mei Xue1, Lu Li2, Bertrand Tremolet de Villers3, Huajun Shen1, Jinfeng Zhu1, Zhibin Yu2, Adam Z. Stieg4, Qibing Pei2, Benjamin J. Schwartz3,4, and Kang L. Wang1,2

1Device Research Laboratory, Department of Electrical Engineering, 2Department of Material Science, 3Department of Chemistry and Biochemistry, 4California NanoSystems Institute, University of California, Los Angeles, CA 90095

Organic solar cells (OSCs) are of great interest for cost-effective photovoltaic as alternative energy resources since they have a strong potential to reduce the cost of photovoltaic cells. However, due to the short exciton diffusion length, OSCs still have low efficiency comparing to silicon-based pn-junction solar cells. In this work, to understand Ag nanoparticle plasmonic effects on organic solar cell for high efficiency hybrid plasmonic organic solar cell, we examined the properties of hybrid P3HT:PCBM:Ag NP solar cells. The measured absorption spectrum shows the increasing of the intensity by around 28% as well as the broadening of the spectrum. The photoinduced charge extraction with a linearly increasing voltage (photo-CELIV) shows that the addition of Ag NPs into the active layer significantly enhances carrier mobility but decreases the total extracted carrier density. Atomic force microscopy (AFM) shows that the Ag NPs tend to phase segregate from the organic material at high concentrations. This suggests that the enhanced mobility results from carriers traversing a Ag NP sub-network, and that the reduced carrier density results from increased recombination from carriers trapped on the Ag particles that cannot easily hop back into the organic phase. These findings help identify the key areas for performance improvement of the hybrid plasmonic cells.
*This work is supported in part by KACST/California Institute of Excellence on Green Nanotechnology.


Graphene Electronics at the FENA Center

Kosmas Galatsis, Philip Kim and Kang L Wang

Center on Functional Engineered Nano Architectonics
University of California, Los Angeles, USA

The Center on Functional Engineered Nano Architectonics (FENA) is one of six Centers of Excellence in the Focus Center Research Program (FCRP) funded by Semiconductor and Defense industry members together with DoD DARPA. FENA is made up of over 34 faculty and over 60 students at over 14 highly distinguished US universities and aims to:

“Discover new nanoelectronics materials and physical processes of devices, which enable extensible information processing systems with enhanced functionality and to create new applications for the semiconductor and defense industries.”

As physical dimensional and electrostatic limits are approached, there are many important fundamental issues faced by scaling CMOS and limiting nanosystems. Among the most significant are: (i) low current drive regardless of the kind of nanodevice, (ii) short channel and other device performance problems in scaled CMOS, (iii) power management due to leakage and the ever-increasing circuit density for functionalities, (iv) massive numbers of interconnections resulting in increased power dissipation, (v) increasing difficulty of traditional top down lithography to reduce feature size and size fluctuations in fabrication and contacts, resulting in lower yield and increased manufacturing cost, (vi) quantum fluctuations of carriers and thermal instability of nanoscale structures, resulting in manufacturing variability. Carbon electronics holds much promise to answer some of these shortfalls and as such will be presented in our poster. This poster will primarily focus on FENA Theme 3 – Carbon Electronics. This FENA theme is aimed at exploring the unique properties of single layer carbon-based materials for novel devices based on atomic layer coupling, spatial confinement, and other quantum and many body effects (e.g., Klein tunneling, coupling of bilayers) at the atomic scale. This theme also incorporates correlated electron nanomaterials with graphene for electric field controlled nonvolatile logic and memory. Key highlights and progress will be presented.


Wafer-Scale Aligned Nanotube Nanoelectronics

Chuan Wang, Jialu Zhang, Xue Lin, Yuchi Che, Jia Liu, Chongwu Zhou*
Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, USA
E-mail:; Tel.: 213 740 4708

Carbon nanotubes hold great potential but also face significant challenges for future electronic applications. In this talk, we report our recent work on wafer-scale assembly and integration of massive aligned nanotubes for nanoelectronics. Massive aligned nanotubes were synthesized over complete 4 inch quartz and sapphire substrates, and then transferred to Si/SiO2 substrates. CMOS analogous fabrication was performed to yield submicron high performance transistors and defect-tolerant logic circuits. Other essential technology components including high density aligned nanotubes with density up to 55 tubes/µm and metal contact engineering for air-stable n-type nanotube transistors and CMOS integrated circuits will also be presented.

Besides, in order to achieve predictable and uniform device performance for large scale integrated circuits, it is important to control the type and chirality of the carbon nanotubes. We have developed a technique to achieve metal-to-semiconductor conversion of carbon nanotubes induced by light irradiation, which is capable of yielding improvements in the current on/off ratio up to 5 orders of magnitude in nanotube-based field-effect transistors. In addition, we have observed that predominantly semiconducting nanotubes can be synthesized under optimized chemical vapor deposition (CVD) conditions, yielding nanotube-based transistors with significantly improved current on/off ratios. Furthermore, we will report our progress on chirality-controlled nanotube CVD growh, yielding aligned nanotubes with predominant single chirality.

Our aligned nanotube platform could serve as critical foundation for future nanotube-based integrated circuits.

Keywords: aligned carbon nanotubes, transistors, integrated circuits, nanoelectronics


[1] “Metal Contact Engineering and Registration-Free Fabrication of CMOS Integrated Circuits using Aligned Carbon Nanotubes”, Chuan Wang, Ryu Koungmin, Alexander Badmaev, Jialu Zhang, Chongwu Zhou, ACS Nano, Vol. 5, 1147, 2011.
[2] “Synthesis and Device Applications of High-Density Aligned Carbon Nanotubes Using Low-Pressure Chemical Vapor Deposition and Stacked Multiple Transfer”, Chuan Wang, Ryu Koungmin, Lewis Gomez, Chongwu Zhou et al., Nano Research, Vol. 3, 831, 2010.
[3] “CMOS-analogous wafer-scale nanotube-on-insulator approach for submicron devices and integrated circuits using aligned nanotubes”, Ryu Koungmin, Alexander Badmaev, Chuan Wang, Chongwu Zhou et al., Nano Letters, Vol. 9, 189, 2009.
[4] “Scalable Light-Induced Metal to Semiconductor Conversion of Carbon Nanotubes”, Lewis Gomez, Akshay Kumar, Chongwu Zhou et al., Nano Letters, Vol. 9, 3592, 2009.


Ultrafast Spin Transfer Torque MRAM with Perpendicular Polarizer

P. Khalili Amiri1, G. Rowlands2, T. Rahman3, Z. M. Zeng4, Y.-J. Chen2, H. Zhao3, A. Kovalev4, J. G. Alzate1, P. Upadhyaya1, K. Galatsis1, I. N. Krivorotov2, J.-P. Wang3, H. W. Jiang4, Y. Tserkovnyak4, J. A. Katine5, J. Langer6, K. L. Wang1

1. Department of Electrical Engineering, University of California, Los Angeles, CA, USA;
2. Department of Physics and Astronomy, University of California, Irvine, CA, USA;
3. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA;
4. Department of Physics and Astronomy, University of California, Los Angeles, CA, USA;
5. Hitachi Global Storage Technologies, San Jose, CA, USA;
6. Singulus Technologies, Kahl am Main, Germany;

Magnetoresistive random access memory (MRAM) utilizing spin transfer torque (STT) is of great interest for both embedded and standalone memory applications. It combines high speed, nonvolatility, high density, and high endurance in a single CMOS-compatible memory technology. MgO-based magnetic tunnel junction (MTJ) bits are used as the memory element in STT-RAM, due to their high tunneling magnetoresistance (TMR) ratio and potentially low switching current densities, making it possible to perform read and write operations using CMOS circuitry.

We present and compare three architectures for MTJ memory bits. These include: (i) In-plane I-STT-RAM, where all magnetic layers are in plane; (ii) Perpendicular P-STT-RAM, with fully perpendicular magnetization in all layers; and (iii) Combined C-STT-RAM, where an in-plane free layer is switched by the combined effect from two in-plane and perpendicular polarizers. Due to the large initial spin torque when a current pulse is applied, this structure allows for ultrafast switching with write times <0.5 ns.

We have demonstrated MTJs exhibiting write times down to ~150 ps. Measurement results indicate that both in-plane and perpendicular junctions contribute to switching, and that the switching time and energy can be reduced by increasing the effect of spin transfer torque from each of the two polarizers. We discuss the effect of material choices on device performance, as well as system implications. Due to its short write times, significantly surpassing those of other MRAM architectures, as well as nonmagnetic memories such as SRAM and DRAM, C-STT-RAM is a promising candidate for nonvolatile embedded memory applications with high speed requirements.


SpinFET Development at the Western Institute Of Nanoelectonics (WIN)

Kosmas Galatsis, Yi Zhou and Kang L Wang

Western Institute of Nanoelectronics
University of California, Los Angeles, USA

The Nanoelectronics Research Initiative (NRI), a consortium of companies in the Semiconductor Industry Association, is seeking to accelerate research in nanoelectronics for the benefit of the semiconductor industry. Semiconductor Research Corporation has formed a subsidiary -- Nanoelectronics Research Corporation (NERC) - to administer the NRI research program. The fifteen-year goal of NRI is to demonstrate novel computing devices with critical dimensions below 10 nanometers and to exercise them in simple computer circuits. These results will enable the semiconductor industry to extend Moore's Law far beyond the year 2020 when the potential limits of the current industry technology known as CMOS may be approached.

As part of the NRI program, the WIN Center was established in 2006 to specifically focus on spin based emerging devices for logic, memory and interconnect applications. WIN aims to be the leading nanoelectronics research Institute able to support the semiconductor, aerospace & defense, health care, biotechnology and telecommunication industries. One major effort underway is research focusing on next generation nanoelectronic systems includes the SpinFET device.

This poster will specifically report on the first experimental demonstration of electrical spin injection, transport and detection in bulk germanium (Ge) towards the realization of a SpinFET. The non-local magnetoresistance in n-type Ge is observable up to 225K. Our results indicate that the spin relaxation rate in the n-type Ge is closely related to the momentum scattering rate, which is consistent with the predicted Elliot-Yafet spin relaxation mechanism for Ge. The bias dependence of the nonlocal magnetoresistance and the spin lifetime in n-type Ge will also be presented along with practical device and circuit implications.


Transport properties of single and bilayer graphene samples at extremely high carrier densities

Dmitri Efetov, Patrick Maher, Simas Glinskis and Philip Kim
Columbia University, New York, NY, USA

Since its discovery in 2004 [1,2] the properties of graphene and its multilayers have been extensively studied at Fermi energies εF close to the charge neutrality point (CNP), where its transport properties and scattering mechanism are thoroughly explained. Due to the dielectric breakdown of SiO2 gate dielectric commonly used in most experiment, graphene's transport properties remain almost entirely unstudied at higher εF > 0.3 eV. In this “metallic” regime, many properties are predicted to be strongly renormalized, where single layer graphene is predicted to become superconducting [3], and in multilayer graphene additional higher energy subbands are expected [4].

Here we report on the temperature dependent electron transport in graphene at different carrier densities n. Employing an poly(ethylene)oxide-LiClO4 electrolytic gate [5], we demonstrate that n can be adjusted up to n=4x1014 cm2 [6]. The measured sample resistivity ρxx increases linearly with temperature T in the high temperature limit, indicating that a quasi-classical phonon distribution is responsible for the electron scattering [7-9]. As T decreases, the resistivity decreases more rapidly following ρxx (T) ~ T4. This low temperature behavior can be described by a Bloch-Grueneisen model taking into account the quantum distribution of the two-dimensional acoustic phonons in graphene. We map out the density dependence of the characteristic temperature ΘBG defining the cross-over between the two distinct regimes, and show, that for all n, ρxx (T) scales as a universal function of the normalized temperature T/ ΘBG.

Furthermore we report on a low temperature transport study of bilayer graphene at high carrier densities [10]. Employing a similar electrolyte gate, we demonstrate the filling of the high energy subbands in bilayer graphene samples at carrier densities n > 2.4x1013 cm2. These subbands, although theoretically predicted [4] and revealed in ARPES studies [11], have so far remained inaccessible and thus uncharacterized by transport studies. As expected from a tight-binding description of the bilayer graphene band structure, we find that the onset density of these subbands can be varied by tuning the bilayer interlayer asymmetry, and is marked by an overall increase of the sample resistivity by ~10%, along with the onset of Shubnikov-de Haas oscillations. From simultaneous Hall and magnetoresistance measurements, as well as SdH oscillations in the “two-fluid” regime, we deduce the carrier densities and mobilities for the higher energy bands separately.

[1] A.K. Geim and K.S. Novoselov, Nature Materials 6, 183 (2007).
[2] A.K. Geim and P. Kim, Scientific American 298, 68 (2008).
[3] J. L. McChesney, Aaron Bostwick, Taisuke Ohta, Thomas Seyller, Karsten Horn, J. González, and Eli Rotenberg, Phys. Rev. Lett. 104, 136803 (2010).
[4] E. McCann, Phys. Rev. B \textbf{74}, 161403 (2006).
[5] Matthew J. Panzer, C. Daniel Frisbie, Advanced Materials 20, 3177 - 3180 (2008)
[6] Dmitri K. Efetov and Philip Kim, Phys. Rev. Lett. 105, 256805 (2010).
APS Viewpoint, Physics 3, 106 (2010).
[7] J.H. Chen, C. Jang, S. Xiao, M. Ishigami, M. S. Fuhrer, Nature Nano. 3, 206 - 209 (2008).
[8] S. V. Morozov, K. S. Novoselov, M. I. Katsnelson, F. Schedin, D. C. Elias, J. A. Jaszczak, and A. K. Geim, Phys. Rev. Lett. 100, 016602 (2008).
[9] E.H. Hwang and S. Das Sarma, Phys. Rev. B 77, 115449 (2008).
[10] Dmitri K. Efetov, Patrick Maher, Simas Glinskis and Philip Kim, to be submitted to Phys. Rev. Lett. End of January 2011.
[11] T. Ohta, A. Bostwick, T. Seyller, K. Horn, and E. Rotenberg, Science 313, 951 (2006).


Enhanced Interfacial Contact Resistance of Organized Single-Walled Carbon Nanotube Interconnect Structures by Purification Methods

Young Lae Kima,d, Hyun Young Jungb,d, Swastik Karc, and Yung Joon Jungb,d

aDepartment of Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts 02115, USA
bDepartment of Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts 02115, USA
cDepartment of Physics, Northeastern University, Boston, Massachusetts 02115, USA
dCenter for High-rate Nanomanufacturing, Northeastern University, Boston, Massachusetts 02115, USA

A method is presented for significantly reducing the interfacial contact resistance of single-walled carbon nanotube (SWCNT) interconnect test-structures. Conventional lithographic cleaning steps are insufficient for complete removal of lithographic residues in SWCNT networks, leading to large interfacial contact resistance. Using improved purification procedures and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au were found to reach values below 2% of the overall resistance in two-probe test-structures of SWCNTs, demonstrating the importance of cleaning lithographic residues from the surface of SWCNTs before the fabrication of metal electrodes. These low-resistance contacts are quite stable over a large temperature range, and represent a step towards the implementation of SWCNTs as future interconnects.

Presenter: Young Lae Kim – Email:


Directed Assembly of Nanoparticles for Fabricating Nanoscale Interconnects

C. Yilmaz, J. Huang, T.H. Kim, G. Goutzamanidis, S. Somu and A. A. Busnaina

NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing (CHN),

Northeastern University, Boston, MA 02115

Fabricating in plane and out of plane interconnects at the nanoscale employing conventional electroplating method has reached a blockade. For further developments in the interconnect technology associated with scaling down needs to be addressed in the large-scale CMOS integration process. In this paper, a fast, highly scalable, room temperature and environmentally friendly nanomanufacturing process for fabricating 3D metallic interconnects from nanoparticles suspended in a solution is presented. Nanoparticles are precisely assembled into prefabricated vias on a wafer and are fused. To achieve this, a controlled dynamic electric field is applied between the wafer with vias and a reference electrode placed far away from them. No post processing is needed to fuse the nanoparticles as it happens during assembly. The results show that using 5nm Au nanoparticles, Au nanopillar (down to 25nm diameter) arrays has been fabricated over 40x40 µm area. For comparison, electroplated Au nanopillars with the same dimensions has been fabricated and tested. Electrical measurements (I-V) on the fabricated nanoparticle based nanopillars as well as electroplated nanopillars have been conducted using Zyvex in-situ nanomanipulator. Resistivity values an order of magnitude higher than gold bulk resistivity has been obtained for both nanoparticle based and electroplated nanorods.


Functionalized SWNT Networks for Micro Chemical Sensors

A. Datar, J. Huang, S. Somu, Y.L. Kim,
Y.J Jung and A. A. Busnaina
The NSF Nanoscale Science and Engineering Center for High-rate

Nanomanufacturing, Northeastern University, Boston, MA

We have developed, fabricated and tested a robust micron scale single wall carbon nanotube (SWNT) based selective chemical sensor. The principle of operation of these SWNT based chemical sensors is conductance based. The SWNTs network with functional groups sensitive to the targeted chemicals serve as the conductance channel of this device. Template guided fluidic assembly is employed to assemble SWNT on prefabricated channels. Initial measurements indicate that these sensors have limit of detection down to ppm and is very selective to the specific analyte of interest in different harsh environments. These sensors exhibited recovery and can be used several thousand times. It had response time in the order of a few seconds making them suitable for portable onsite detection. Modification of the SWNT functionalization can lead to simple yet versatile sensors for detection of various chemicals.


Modulating the Performance of Carbon Nanotube Field-Effect Transistors via Rose Bengal Molecular Doping

J. Huang, A. Datar, S. Somu, A. A. Busnaina

NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing, Northeastern University, Boston MA 02115

We report on modulating the performance of carbon nanotube field-effect transistors (CNTFETs) by rationally selecting doping molecules. A large shift in threshold voltage, improved subthreshold swing, and controllable hysteresis direction are simultaneous observed due to this doping. We show that Rose Bengal sodium salt (RB-Na) molecular doping can effectively shift the threshold voltage (∆Vth) of CNTFETs up to ~ 6 V, decrease the subthreshold swing to130 mV/dec, increase the effective field-effect mobility to 5 cm2V-1s-1, and change the hysteresis direction. This room temperature chemical doping approach provides an efficient, simple, and cost-effective method to fabricate highly reliable and high-performance nanotube transistors for future nanotube based electronics.


Large-Area Automatic Graphene Identification and Quality Control: Prospects of Industrial Applications

Craig M. Nolen(1), Giovanni Denina(2), Desalegne Teweldebrhan(1), Bir Bhanu(2), Alexander A. Balandin(1)
(1): Department of Electrical Engineering and Materials Science and Engineering Program, Nano-Device Laboratory, Bourns College of Engineering, University of California - Riverside, Riverside, California 92521 USA
(2): Department of Electrical Engineering, Visualization and Intelligent Systems Laboratory, Bourns College of Engineering, University of California Riverside, Riverside, California 92521, USA.

Graphene has been gaining increasing attention from the research community and electronic semiconductor industry due to its extraordinary electronic, thermal, and mechanical properties. Current microscopy methods for graphene layer identification are limited; many of them are destructive and restricted to small-area identification, which is not practical for scaled-up industrial needs. Most recently, significant progress has been made in large-area graphene exfoliation, chemical vapor deposition (CVD), and chemical exfoliation. Intrinsic properties of this material undergo strong modification as the number of atomic layers changes from single layer to bilayer to few-layer. High-throughput large-area reliable layer identification of graphene and assessment of its quality becomes critical for further development of graphene technology. Here we present a method for the graphene layer identification over wafer-sized areas, which is characterized by high accuracy, high throughput and scalability required for industrial metrology use. Our method is based on a fast image processing algorithm, which analyzes optical contrasts between single-layer and few-layer graphene. The method calibration is performed with the local micro-Raman spectroscopic scans. Our data suggests that the proposed technique of layer identification is well suited for graphene nanometrology and automated quality control for both laboratory research and large-scale industrial production.


Graphene Based Thermal Interface Materials for the Next Generation Electronics

Khan M. F. Shahil, Samia Subrina and Alexander A. Balandin
Nano-Device Laboratory, Department of Electrical Engineering and Materials Science and
Engineering Program, Bourns College of Engineering, University of California – Riverside,

Riverside, California, 92521 USA

Increasing power densities and speed of electronic chips with each new technology node stimulate the search for more efficient thermal interface materials (TIMs). Conventional TIMs are based on polymers or greases filled with the thermally conductive particles such as silver, which require high volume fractions of the filler material (up to ~70%) to achieve thermal conductivity of about 1-5 W/mK of the composite. Here we report experimental investigation of epoxy composite TIMs with the liquid phase exfoliated graphene as filler material. Using a surfactant stabilized graphene dispersion method we produced TIMs with graphene as the filler material. The thermal properties of the resulting graphene-epoxy composites have been measured with the “laser flash” technique. The thermal conductivity enhancement factor exceeds ~ 2300% at 10% of the volume loading fraction. This enhancement is larger than anything that has been achieved with other fillers. Computer simulations of thermal properties of TIM composites suggest that graphene can outperform other carbon allotropes and derivatives. Moreover, graphene based TIMs have a number of other advantages related to their viscosity and adhesion, which meet the industry requirements. Our results suggest that graphene can become excellent filler materials in the next generation of TIMs.


Nanomagnet Logic Systems

M.T. Alam, G.H. Bernstein, M. Crocker, A.J. Dingler, X.S. Hu, S.J. Kurtz, S. Liu, J. Nahas,

M.T. Niemier, W. Porod, M.J. Siddiq, E. Varga

Fringing field interactions between magnetic islands can be used to perform Boolean logic operations [1]. Binary information is represented via magnetization state. Presently, five fundamental tenets” [2] that a device must satisfy for use in a digital system have been experimentally demonstrated for nanomagnet logic (NML). A clock modulates the energy barriers between magnetization states in an NML circuit [3]. Recently, experimental demonstrations of individual island switching [4], as well as the re-evaluation of lines and gates with CMOS compatible clock structures [5] have been reported (fields are generated with a line clad with ferromagnetic material [6]). To interface with transistor-based circuitry, a magnetic-electrical interface is needed. Work presented in [7] introduced two designs where fringing fields from an NML device were used to set the free layer of a magnetic tunnel junction. Designs from [7] (and variants thereof) are active experimental targets, and could be repurposed for input (spin torque transfer would set the state of the free layer). A simple biasing line represents an alternative input mechanism. All of the above, energy/performance projections, and outstanding challenges will be highlighted in the context of the SRC NRI MIND center and the DARPA Non-Volatile logic program.

[1] A. Imre, et al., "Majority logic gate for Magnetic Quantum-dot Cellular Automata," Science, vol.
311, pp. 205-208, Jan 13 2006.
[2] R. Waser, Nanoelectronics and information technology: Advanced electronic materials and
novel devices
. Weinheim: Wiley-VCH, 2003.
[3] G. Csaba, et al., "Power dissipation in nanomagnetic logic devices," in 2004 4th IEEE
Conference on Nanotechnology
, 2004, pp. 346-348.
[4] M. T. Alam, et al., "On-Chip Clocking for Nanomagnet Logic Devices," IEEE Transactions on
, vol. 9, pp. 348-351, May 2010.
[5] M. T. Alam, et al., "On-chip Clocking of Nanomagnet Logic Lines and Gates," conditionally
accepted in IEEE T. on Nanotechnology
, 2011.
[6] M. T. Niemier, et al., "Clocking Structures and Power Analysis for Nanomagnet-Based Logic
Devices," International Symposium on Low Power Electronics and Design (ISLPED), pp.
26-31, 2007.
[7] S. Liu, et al., "Magnetic-Electrical Interface for Nanomagnet Logic," IEEE T. on
(to appear), 2010.


Center for Hierarchical Manufacturing: An NSF Nanoscale Science and Engineering Center

P.I. James J. Watkins
Polymer Science and Engineering Department
University of Massachusetts Amherst, Amherst MA 01003

Co-PI Mark T. Tuominen

Physics Department
University of Massachusetts Amherst, Amherst MA 01003

The Center for Hierarchical Manufacturing (CHM) is a leading research and education center for the development of precision and cost efficient process platforms and tools for the manufacturing of next generation, nanotechnology-enabled devices for electronics, energy conversion, resource conservation and human health. The Center’s approach involves the integration of components and systems across multiple length scales and integrates nanofabrication processes for sub-30 nm elements based on directed self-assembly, additive-driven assembly, nanoimprint lithography, and conformal deposition at the nanoscale with Si wafer technologies or high-rate roll-to-roll based production tools. The CHM effort is made comprehensive by research on device design, modeling and prototype testing in functional architectures that take advantage of the specific hierarchical nanomanufacturing capabilities developed by the Center. The CHM hosts and facilitates the National Nanomanufacturing Network (NNN)--a catalyst for U.S. nanomanufacturing-based economic development and research collaboration, a network of manufacturing facilities and expertise, a dynamic web-based information clearinghouse, and a pathway for university-industry-government partnerships. Efforts within the NNN include InterNano, a freely accessible digital library and information clearinghouse on nanomanufacturing. This poster will provide highlights of the CHM’s research accomplishments, education efforts and outreach activities.


Roll-to-Roll Manufacturing of Nanostructured Materials and Devices at the NSF Center for Hierarchical Manufacturing

P.I. James J. Watkins
Polymer Science and Engineering Department
University of Massachusetts Amherst, Amherst MA 01003

Co-PI Mark T. Tuominen
Physics Department
University of Massachusetts Amherst, Amherst MA 01003

The development of cost-effective manufacturing platforms for nanotechnology enabled materials and devices is essential for the transition of laboratory developments to commercial products with economic and societal benefits. The Center for Hierarchical Manufacturing (CHM) is an NSF-funded Nanoscale Science and Engineering Center that focuses on new nanofabrication processes that can be integrated with conventional manufacturing techniques across multiple length scales on Si wafer and roll-to-roll (R2R) process platforms. In this poster we will focus on the CHM’s recent advances in self-assembly, additive drive assembly, and nanoimprint lithography that can yield well-ordered, functional, nanostructured hybrid materials and devices using R2R process platforms that are compatible with the tools of the flexible electronics, advanced coatings and printing industries. Highly-filled, well-ordered polymer-additive nanocomposites containing nanoparticles, fullerenes or other functional components for use in energy storage and conversion devices, flexible electronics and as high magnetic permeability metamaterials will be described. New R2R platforms tools for UV-assisted nanoimprint lithography and R2R coating of ordered hybrid materials have been designed and constructed for use in a CHM test-bed facility and will be discussed.


CVD Graphene Growth on Copper

Xuesong Lia, Yufeng Haoa, Carl W. Magnusona, Luigi Colombob, and Rodney S. Ruoffa

aDepartment of Mechanical Engineering and Materials Science and Engineering, 1 University Station C2200, The University of Texas at Austin, Austin, TX 78712-0292 bTexas Instruments Incorporated, Dallas, TX 75243

Graphene, a two-dimensional monolayer of sp2-bonded carbon atoms, has been attracting great interest due to its distinctive band structure and physical properties. Large-area graphene growth is especially desirable for the production of electronic devices and many other potential applications. We grew large-area single-layer graphene films of the order of centimeters on copper substrates by chemical vapor deposition (CVD) using methane. The low solubility of carbon in copper is responsible to make this growth process self-limiting. This has been confirmed by the carbon isotope labeling in conjunction with Raman spectroscopic mapping techniques. We further investigated the effect of growth parameters such as temperature, methane flow rate and partial pressure on the growth rate, domain size, and surface coverage of graphene. We also developed graphene film transfer processes to arbitrary substrates. Recently, single-crystal graphene with dimension of 0.5mm lateral size has been achieved in our group through Copper enclosure technique based on a CVD process.


INDEX-the Institute for Nanoelectronics Discovery and Exploration

The College of Nanoscale Science and Engineering
The University at Albany-SUNY

Albany, New York, USA

Ji Ung Lee*, James G. Ryan and Alain E. Kaloyeros
*poster presenter

The Institute for Nanoelectronics Discovery and Exploration (“INDEX”) embodies a comprehensive, inter-disciplinary, multi-university, long-term research approach to investigate novel paradigms that transcend electronic charge as a computing device state variable to surmount expected CMOS scaling limits. The INDEX strategic technical focus includes development of the nanomaterial systems, atomic scale fabrication technologies, predictive device, sub-system, and system modeling protocols, power dissipation management designs, and realistic architectural integration schemes for the realization of novel magnetic and molecular quantum devices. INDEX is organized in five synergistic tasks: (1) Novel Computing State-Variable Devices; (2) Self-Assembly and Fabrication; (3) Architecture and Modeling; (4) Theory and Simulation; (5) Strategy and Roadmap, and (6) Metrology and Characterization. INDEX includes a world-class team of investigators in an initial consortium of seven university partners, including Georgia Tech, Harvard University, MIT, Purdue University, RPI, UAlbany, and Yale University. INDEX has generated significant public and private resources to leverage seed funding provided by NERC to ensure the establishment of the state of-the-art facilities and the availability of the funding necessary to perform a systematic and thorough assessment of the device paradigms proposed. The resources leveraged by INDEX include significant funding from the federal government, the states of Georgia and New York, and NERC member companies.


Institute for Nanoelectronics Discovery and Exploration (INDEX): Technical Overview

The College of Nanoscale Science and Engineering
The University at Albany-SUNY

Albany, New York, USA

Ji Ung Lee*, James G. Ryan and Alain E. Kaloyeros
*poster presenters

INDEX program partners leading university researchers with state-of-art fabrication and development facility to explore new logic devices that go beyond the limits imposed by electronic charge as device state variable. INDEX is a comprehensive program that examines the entire system through synergistic examination of new device concepts, self-assembly and fabrication, and circuit architecture with emphasis on scalability, integration and power dissipation. We will provide an overview of INDEX technical programs that encompass theoretical and experimental assessment of new computing state-variables. These device concepts are broadly categorized into: 1) carbon nanotube and graphene based devices that allow reconfigurable logic and new state variables based on interference and ballistic reflection, 2) magnetic devices based on complex oxides and magnetic mulitlayer structures for non-volatile logical switch and multi-bit storage devices, 3) Spintronics based on single spin single-electron transistor, and 4) molecular devices that utilize excitons and molecular conformation to accomplish logic functions.